Techniques for clamping and declamping a substrate

ABSTRACT

Methods of clamping and declamping a wafer from a platen are disclosed. The platen comprises one or more electrodes, which are electrically biased to electrostatically clamp the wafer to the platen. The electrode is biased to a first voltage where the wafer may be processed. Thereafter, one or more voltages are subsequently applied to the electrodes. In some embodiments, each subsequent voltage is less than the previously applied voltage. In other embodiments, one or more of the subsequent voltages may be greater than the previously applied voltage. This sequence of voltage may reduce the likelihood that the wafer will stick or adhere to the platen during the removal process.

This application claims priority of U.S. Provisional Application Ser.No. 61/770,642, filed Feb. 28, 2013, the disclosure of which is hereinincorporated by reference in its entirety.

FIELD

The present disclosure relates to an electrostatic clamp, moreparticularly to a method of clamping and declamping a target on anelectrostatic clamp.

BACKGROUND

Ion implantation process is used in manufacturing electrical and opticaldevices. It is a process by which dopants or impurities are introducedinto a target to alter the target's mechanical, electrical, and/oroptical property. In integrated circuit (IC) device manufacturing, thetarget may be silicon or other semiconductor wafers, or one or morefeatures or films thereon. Generally, the dopants or impurities may haveone or more properties that differ from the properties of the target.Once implanted into a region in the target, the dopants or impuritiesmay alter the region's properties.

During the ion implantation process, the target or the wafer 102 may besupported on a platen 112. As illustrated in FIG. 1, the platen 112 maycomprise one or more electrodes 114 that are electrically connected to apower supply 116. In some embodiments, multiple concentric electrodes114 are provided where one of the electrodes may be an inner electrode114 a and another electrode may be an outer electrode 114 b. In otherembodiments, multiple electrodes are provided at opposite sides of theplaten 112. To electrostatically clamp the wafer 102 onto the platen,the bias voltage may be applied to the electrodes 114. In someembodiments, opposite voltage may be applied to different electrodes.For example, one of the electrodes 114 may be applied with positivevoltage, whereas negative voltage is applied to another electrode 114.The magnitude of the clamping voltage may be the same or different.

Referring to FIG. 2, there is shown timing of the clamping voltageprovided from the power supply 116 to one or more electrodes 114 in theplaten 112. After the wafer 102 is loaded onto the platen 112, clampingvoltage (V₁) is applied to the electrodes 114 at T₁ and the wafer 102 iselectrostatically clamped onto the platen 112. Although not illustrated,those skilled in the art will recognize that if two or more electrodesare provided, one of the electrodes will be applied positive V₁ and theother electrode will be applied with negative V₁. The voltage applied tothe electrodes 114 may be maintained during the ion implantationprocess, and the wafer 102 may remain clamped on the platen 112. Afterthe ion implantation is completed (i.e. T₂), the clamping voltage V₁ isno longer applied to the electrodes 114, and the wafer 102 is removedfrom the platen 112. In some embodiments, the wafer 102 removal processmay include lifting and separating the wafer 102 from the platen 112with lift pins (not shown) and removing the wafer 102 from the platen112. As known in the art, the voltage applied to the electrodes 114 isdifferent from the voltage directly applied to the wafer 102 to processthe wafer 102. For example, in some process, negative voltage is appliedto the wafer 102 to attract positively charged ions. To clamp the wafer102, voltage is applied to the electrodes 114 in the platen 112 toelectrostatically clamp the wafer 102 onto the platen 112. As is alsoknown in the art, a dielectric layer is disposed between the electrodes114 and the wafer 102 to electrically isolate the wafer 102 from theelectrodes 114.

The ion 10 directed and implanted into the wafer 102 may be positivelycharged ions 10. The residual charge in the wafer 102 due to implantingcharged ions may cause at a portion of the wafer 102 to stick to theplaten 112 surface. Unloading such a wafer 102 may be difficult. Also,if a layer of dielectric film is coated on the lower surface of thewafer 102, the neutralization of the charged ions and electrons may bedelayed, thus causing the wafer 102 to remain attached to the platen 112surface even when the clamping voltage has been removed. Attempting toseparate the wafer 102 from the platen 112 surface using excessive forcemay result in wafer breakage. The wafer breakage may be more frequent ifa layer of dielectric film (not shown) is coated on the lower surface ofthe wafer 102.

As such, a new method of clamping and declamping is needed.

SUMMARY

Methods of clamping and declamping a wafer from a platen are disclosed.The platen comprises one or more electrodes, which are electricallybiased to electrostatically clamp the wafer to the platen. The electrodeis biased to a first voltage where the wafer may be processed.Thereafter, one or more voltages are subsequently applied to theelectrodes. In some embodiments, each subsequent voltage is less thanthe previously applied voltage. In other embodiments, one or more of thesubsequent voltages may be greater than the previously applied voltage.This sequence of voltage may reduce the likelihood that the wafer willstick or adhere to the platen during the removal process.

In one embodiment, the method of clamping and declamping a wafer from aplaten comprises placing the wafer on the platen, where the platencomprises an electrode for clamping the wafer onto the platen, while theelectrode is biased at an initial voltage; applying a first voltage tothe electrode of the platen to electrostatically clamp the wafer to theplaten, the first voltage greater than the initial voltage; applying asecond voltage to the electrode, the second voltage less than the firstvoltage and greater than the initial voltage; and removing the waferfrom the platen after the application of the second voltage to theelectrode.

In another embodiment, the method of clamping and declamping a waferfrom a platen comprises placing the wafer on the platen where the platencomprising an electrode for clamping the wafer onto the platen, whilethe electrode is biased at an initial voltage; applying a first voltageto the electrode to electrostatically clamp the wafer to the platen, thefirst voltage greater than the initial voltage; applying a secondvoltage to the electrode, lower than the first voltage and greater thanthe initial voltage; applying a third voltage, higher than the secondvoltage and lower than the first voltage, to the electrode; and removingthe wafer after application of the third voltage to the electrode.

In another embodiment, the method of clamping and declamping a waferfrom a platen comprises placing the wafer on the platen, the platencomprising an electrode for clamping the wafer, while the electode isbiased at 0 volts; applying a first voltage to the electrode toelectrostatically clamp the wafer to the platen, the first voltagebetween 100V and 1000V; applying a second voltage to the electrode, thesecond voltage less than the first voltage and between 5V and 600V;applying a third voltage to the electrode after application of thesecond voltage, wherein the third voltage is less than the secondvoltage and between 5V and 600 V; and removing the wafer from the platenafter the application of the third voltage to the electrode.

BRIEF DESCRIPTION OF THE FIGURES

For a better understanding of the present disclosure, reference is madeto the accompanying drawings, which are incorporated herein by referenceand in which:

FIG. 1 shows an exemplary system for clamping and declamping a wafer toa platen according to the prior art;

FIG. 2 shows a timing diagram that may be used with the system of FIG. 1according to the prior art;

FIG. 3 shows a timing diagram that can be applied to the system of FIG.1 according to one embodiment;

FIG. 4 shows a timing diagram that can be applied to the system of FIG.1 according to a second embodiment;

FIG. 5 shows a timing diagram that can be applied to the system of FIG.1 according to a third embodiment; and

FIG. 6 shows a timing diagram that can be applied to the system of FIG.1 according to a fourth embodiment.

DETAILED DESCRIPTION

The present disclosure will now be described in more detail withreference to particular embodiments thereof as shown in the accompanyingdrawings. While the present disclosure is described below with referenceto particular embodiments, it should be understood that the presentdisclosure is not limited thereto.

Referring to FIG. 3, there is shown an exemplary method of clamping anddeclamping a wafer according to one embodiment of the presentdisclosure. In this figure, the method is described with respect to thetiming of the clamping voltage provided from the power supply 116 to oneor more electrodes 114 in the platen 112. For clarity and simplicity,the method of the present embodiment will be described with respect tocomponents shown in FIG. 1. As such, the method of the presentembodiment should be understood in relation to FIG. 1.

In the present embodiment, the wafer 102 may be loaded onto the platen112. Thereafter, at T₁, the electrodes 114 in the platen 112 may beapplied with a first voltage V₁, and the wafer 102 may beelectrostatically clamped onto the platen 112. Prior to applying thefirst voltage V₁, the electrodes 114 may be applied with V₀. In thepresent disclosure, the V₀ may be zero voltage or some other voltageless than V₁. In the present disclosure, the first voltage V₁ may be theclamping voltage, and the voltage may be in the range of about 100 V toabout 1 kV. In one embodiment, the first voltage may be about 150 V. Inanother embodiment, the first voltage may be about 250 V. In anotherembodiment, the first voltage may be about 500 V. Yet in anotherembodiment, the first voltage may be about 750 V. If the platencomprises inner and outer electrodes 114 a and 114 b, one of theelectrodes 114 a and 114 b may be applied with positive first voltage V₁and the other one of the electrodes 114 a and 114 b may be applied withnegative first voltage. The first voltage V₁ may be maintained until T₂as illustrated in the figure, when a second voltage V₂ is applied to theelectrodes 114. Between T₁ and T₂, the ion implantation process isperformed.

As illustrated in FIG. 3, the second voltage V₂ applied to the electrode114 may be less than the first voltage V₁. For example, the secondvoltage V₂ may range from about 5 V to about 100 V. In one embodiment,the second voltage V₂ may be about 5 V. In another embodiment, thesecond voltage V₂ may be about 15 V. In another embodiment, the secondvoltage V₂ may be about 25 V. Yet in another embodiment, the secondvoltage V₂ may be about 35 V.

After T₂, the process to dechuck/remove the wafer 102 from the platen112 may be performed. For example, the wafer 102 may be dechucked fromthe platen 112 and the wafer 102 may be removed from the platen 112 atT₂ or after T₂. For example, the process to dechuck/remove the wafer 102from the platen 114 may be performed at or after T₂, when the electrodes114 are applied with the second voltage V₂ that is less than the firstvoltage V₁, but greater than V₀ applied to the electrodes prior to T₁.In one embodiment, the process may be performed at or after T_(f) whenV₀ is applied to the electrodes 114.

Referring to FIG. 4, there is shown another exemplary method of clampingand declamping a wafer according to another embodiment of the presentdisclosure. In this figure, the method is described with respect to thetiming of the clamping voltage provided from the power supply 116 to oneor more electrodes 114 in the platen 112. For clarity and simplicity,the method of the present embodiment will be described with respect tocomponents shown in FIG. 1. As such, the method of the presentembodiment should be understood in relation to FIG. 1.

In the present embodiment, the wafer 102 may be loaded onto the platen112. Thereafter, at T₁, the electrodes 114 in the platen 112 may beapplied with a first voltage V₁, and the wafer 102 may beelectrostatically clamped onto the platen 112. Prior to applying thefirst voltage V₁, the electrodes 114 may be applied with V₀. In thepresent disclosure, the V₀ may be zero voltage or some other voltageless than V₁. In the present disclosure, the first voltage V₁ may be theclamping voltage, and the voltage may be in the range of about 100 V toabout 1 kV. In one embodiment, the first voltage may be about 150 V. Inanother embodiment, the first voltage may be about 250 V. In anotherembodiment, the first voltage may be about 500 V. Yet in anotherembodiment, the first voltage may be about 750 V. If the platencomprises inner and outer electrodes 114 a and 114 b, one of theelectrodes 114 a and 114 b may be applied with positive first voltage V₁and the other one of the electrodes 114 a and 114 b may be applied withnegative first voltage. The first voltage V₁ may be maintained until T₂as illustrated in the figure, when a second voltage V₂ is applied to theelectrodes 114. Between T₁ and T₂, the ion implantation process isperformed.

As illustrated in FIG. 4, the second voltage V₂ applied to the electrodemay be less than the first voltage V₁, but greater than V₀. In thepresent embodiment, the second voltage V₂ may be any voltage rangingfrom about 75 V to about 800 V. In one example, the second voltage maybe about 100 V. In another example, the second voltage may be about 150V. In another example, the second voltage may be about 300 V. In anotherexample, the second voltage may be about 400 V. In another example, thesecond voltage may be about 500 V. Yet in another example, the secondvoltage may be about 600 V.

The second voltage V₂ may be applied to the electrodes 114 until T₃ whenthe electrodes 114 in the platen 112 are applied with a third voltageV₃. In the present embodiment, the third voltage V₃ applied to theelectrode may be less than the second voltage V₂, but greater than V₀.In the present embodiment, the third voltage V₃ may be any voltageranging from about 50 V to about 600 V. In one example, the thirdvoltage V₃ may be about 80 V. In another example, the third voltage V₃may be about 150 V. In another example, the third voltage V₃ may beabout 300 V. In another example, the third voltage V₃ may be about 450V. In another example, the third voltage V₃ may be about 500 V. Yet inanother example, the third voltage V₃ may be about 550 V.

The third voltage V₃ may be applied to the electrodes 114 until T₄ whenthe electrodes 114 in the platen 112 are applied with a fourth voltageV₄. In the present embodiment, the fourth voltage V₄ applied to theelectrode may be less than the third voltage V₃, but greater than V₀. Inthe present embodiment, the fourth voltage V₄ may be any voltage rangingfrom about 25 V to about 500 V. In one example, the fourth voltage V₄may be about 25 V. In another example, the fourth voltage V₄ may beabout 75 V. In another example, the fourth voltage V₄ may be about 100V. In another example, the fourth voltage V₄ may be about 200 V. Inanother example, the fourth voltage V₄ may be about 300 V. Yet inanother example, the second voltage may be about 400 V. The fourthvoltage V₄ may be applied to the electrodes 114 until T₅ when theelectrodes 114 in the platen 112 are applied with a fifth voltage V₅. Inthe present embodiment, the fifth voltage V₅ applied to the electrodemay be less than the fourth voltage V₄, but greater than V₀. In thepresent embodiment, the fifth voltage V₅ may be any voltage ranging fromabout 5 V to about 50 V. In one example, the fifth voltage V₅ may beabout 10 V. In another example, the fifth voltage V₅ may be about 15 V.In another example, the fifth voltage V₅ may be about 30 V. In anotherexample, the fifth voltage V₅ may be about 50 V. In another example, thefifth voltage V₅ may be about 75 V. Yet in another example, the fifthvoltage V₅ may be about 100 V. The fifth voltage V₅ may be applied untilT_(f) when V₀ is applied to the electrodes 114.

After T₂, the process to dechuck/remove the wafer 102 from the platen112 may be performed. For example, the wafer 102 may be dechucked fromthe platen 112 and the wafer 102 may be removed from the platen 112 atT₂ of after T₂. In particular, the process to dechuck/remove the wafer102 from the platen 114 may be performed at T₂, T₃, T₄, T₅ or T_(f).

Referring to FIG. 5, there is shown another exemplary method of clampingand declamping a wafer according to another embodiment of the presentdisclosure. In this figure, the method is described with respect to thetiming of the clamping voltage provided from the power supply 116 to oneor more electrodes 114 in the platen 112. For clarity and simplicity,the method of the present embodiment will be described with respect tocomponents shown in FIG. 1. As such, the method of the presentembodiment should be understood in relation to FIG. 1.

In the present embodiment, the wafer 102 may be loaded onto the platen112. Thereafter, at T₁, the electrodes 114 in the platen 112 may beapplied with a first voltage V₁, and the wafer 102 may beelectrostatically clamped onto the platen 112. Prior to applying thefirst voltage V₁, the electrodes 114 may be applied with V₀. In thepresent disclosure, the V₀ may be zero voltage or some other voltageless than V₁. In the present disclosure, the first voltage V₁ may be theclamping voltage, and the voltage may be in the range of about 100 V toabout 1 kV. In one embodiment, the first voltage may be about 150 V. Inanother embodiment, the first voltage may be about 250 V. In anotherembodiment, the first voltage may be about 500 V. Yet in anotherembodiment, the first voltage may be about 750 V. If the platencomprises inner and outer electrodes 114 a and 114 b, one of theelectrodes 114 a and 114 b may be applied with positive first voltage V₁and the other one of the electrodes 114 a and 114 b may be applied withnegative first voltage. The first voltage V₁ may be maintained until T₂as illustrated in the figure, when a second voltage V₂ is applied to theelectrodes 114. Between T₁ and T₂, the ion implantation process isperformed.

At T₂, the second voltage V₂ applied to the electrodes 114. The secondvoltage V₂ in the present embodiment may be less than the first voltageV₁, but greater than V₀. In the present embodiment, the second voltageV₂ may be any voltage ranging from about 5 V to about 600 V. In oneexample, the second voltage may be about 15 V. In another example, thesecond voltage may be about 50 V. In another example, the second voltagemay be about 75 V. In another example, the second voltage may be about100 V. In another example, the second voltage may be about 150 V. Yet inanother example, the second voltage may be about 300 V.

The second voltage V₂ may be applied to the electrodes 114 until T₃ whenthe electrodes 114 in the platen 112 are applied with a third voltageV₃. In the present embodiment, the third voltage V₃ applied to theelectrode may be greater than the second voltage V₂, but less than thefirst voltage V₁. In the present embodiment, the third voltage V₃ may beany voltage ranging from about 50 V to about 400 V. In one example, thethird voltage V₃ may be about 75 V. In another example, the thirdvoltage V₃ may be about 150 V. In another example, the third voltage V₃may be about 250 V. In another example, the third voltage V₃ may beabout 350 V. In another example, the third voltage V₃ may be about 400V. Yet in another example, the third voltage V₃ may be about 450 V.

The third voltage V₃ may be applied to the electrodes 114 until T₄ whenthe electrodes 114 in the platen 112 are applied with a fourth voltageV₄. In the present embodiment, the fourth voltage V₄ applied to theelectrode may be less than the third voltage V₃, but greater than V₀. Inthe present embodiment, the fourth voltage V₄ may be equal to the secondvoltage V₂. However, the present disclosure does not preclude the fourthvoltage being greater or less than the second voltage V₂. In the presentembodiment, the fourth voltage V₄ may be any voltage ranging from about25 V to about 600 V. In one example, the fourth voltage V₄ may be about15 V. In another example, the fourth voltage V₄ may be about 50 V. Inanother example, the fourth voltage V₄ may be about 75 V. In anotherexample, the fourth voltage V₄ may be about 100 V. In another example,the fourth voltage V₄ may be about 150 V. Yet in another example, thefourth voltage V₄ may be about 300 V.

In the present embodiment, the fourth voltage V₄ may be applied to theelectrodes 114 until T_(f) when the electrodes 114 in the platen 112 areapplied with V₀.

After T₂, the process to dechuck/remove the wafer 102 from the platen112 may be performed. Although the wafer 102 dechucking/removing processmay be performed any time after T₂, the process may preferably performedafter T₄, or any time after the third voltage V₃ higher than the secondvoltage V₂ is applied.

Referring to FIG. 6, there is shown another exemplary method of clampingand declamping a wafer according to another embodiment of the presentdisclosure. In this figure, the method is described with respect to thetiming of the clamping voltage provided from the power supply 116 to oneor more electrodes 114 in the platen 112. For clarity and simplicity,the method of the present embodiment will be described with respect tocomponents shown in FIG. 1. As such, the method of the presentembodiment should be understood in relation to FIG. 1.

In the present embodiment, the wafer 102 may be loaded onto the platen112. Thereafter, at T₁, the electrodes 114 in the platen 112 may beapplied with a first voltage V₁, and the wafer 102 may beelectrostatically clamped onto the platen 112. Prior to applying thefirst voltage V₁, the electrodes 114 may be applied with V₀. In thepresent disclosure, the V₀ may be zero voltage or some other voltageless than V₁. In the present disclosure, the first voltage V₁ may be theclamping voltage, and the voltage may be in the range of about 100 V toabout 1 kV. In one embodiment, the first voltage may be about 150 V. Inanother embodiment, the first voltage may be about 250 V. In anotherembodiment, the first voltage may be about 500 V. Yet in anotherembodiment, the first voltage may be about 750 V. If the platencomprises inner and outer electrodes 114 a and 114 b, one of theelectrodes 114 a and 114 b may be applied with positive first voltage V₁and the other one of the electrodes 114 a and 114 b may be applied withnegative first voltage. The first voltage V₁ may be maintained until T₂as illustrated in the figure, when a second voltage V₂ is applied to theelectrodes 114. Between T₁ and T₂, the ion implantation process isperformed.

At T₂, the second voltage V₂ applied to the electrodes 114. The secondvoltage V₂ in the present embodiment may be less than the first voltageV₁, but greater than V₀. In the present embodiment, the second voltageV₂ may be any voltage ranging from about 5 V to about 600 V. In oneexample, the second voltage may be about 15 V. In another example, thesecond voltage may be about 50 V. In another example, the second voltagemay be about 150 V. In another example, the second voltage may be about250 V. In another example, the second voltage may be about 350 V. Yet inanother example, the second voltage may be about 450 V.

The second voltage V₂ may be applied to the electrodes 114 until T₃ whenthe electrodes 114 in the platen 112 are applied with a third voltageV₃. In the present embodiment, the third voltage V₃ applied to theelectrode may be less than the second voltage V₂, but greater than V₀.In the present embodiment, the third voltage V₃ may be any voltageranging from about 5 V to about 600 V. In one example, the third voltageV₃ may be about 15 V. In another example, the third voltage V₃ may beabout 50 V. In another example, the third voltage V₃ may be about 75 V.In another example, the third voltage V₃ may be about 100 V. In anotherexample, the third voltage V₃ may be about 150 V. Yet in anotherexample, the third voltage V₃ may be about 300 V.

The third voltage V₃ may be applied to the electrodes 114 until T₄ whenthe electrodes 114 in the platen 112 are applied with a fourth voltageV₄. In the present embodiment, the fourth voltage V₄ applied to theelectrodes 114 may be greater than the third voltage V₃, but less thanthe first voltage V₁. In the present embodiment, the fourth voltage V₄may be equal to the second voltage V₂. However, the present disclosuredoes not preclude the fourth voltage V₄ being greater or less than thesecond voltage V₂. In the present embodiment, the fourth voltage V₄ maybe any voltage ranging from about 5 V to about 600 V. In one example,the fourth voltage V₄ may be about 15 V. In another example, the fourthvoltage V₄ may be about 50 V. In another example, the fourth voltage V₄may be about 150 V. In another example, the fourth voltage V₄ may beabout 250 V. In another example, the fourth voltage V₄ may be about 350V. Yet in another example, the fourth voltage V₄ may be about 450 V.

The fourth voltage V₄ may be applied to the electrodes 114 until T₅ whenthe electrodes 114 in the platen 112 are applied with a fifth voltageV₅. In the present embodiment, the fifth voltage V₅ applied to theelectrodes 114 may be less than the fourth voltage V₄, but greater thanV₀. In the present embodiment, the fifth voltage V₅ may be equal to thethird voltage V₃. However, the present disclosure does not preclude thefifth voltage V₅ being greater or less than the third voltage V₃.

After T₂, the process to dechuck/remove the wafer 102 from the platen112 may be performed. Although the wafer 102 dechucking/removing processmay be performed any time after T₂, the process may preferably performedafter T₃ or T₅, or any time after the fourth voltage V₄ higher than thethird voltage V₃ is applied.

Herein, techniques for chucking and dechucking a wafer during waferprocessing process are disclosed. The present disclosure is not to belimited in scope by the specific embodiments described herein. Indeed,other various embodiments of and modifications to the presentdisclosure, in addition to those described herein, will be apparent tothose of ordinary skill in the art from the foregoing description andaccompanying drawings. Thus, such other embodiments and modificationsare intended to fall within the scope of the present disclosure.Further, although the present disclosure has been described herein inthe context of a particular implementation in a particular environmentfor a particular purpose, those of ordinary skill in the art willrecognize that its usefulness is not limited thereto and that thepresent disclosure may be beneficially implemented in any number ofenvironments for any number of purposes. Accordingly, the claims setforth below should be construed in view of the full breadth and spiritof the present disclosure as described herein.

What is claimed is:
 1. A method of clamping and declamping a wafer froma platen, comprising: placing said wafer on said platen, said platencomprising an electrode for clamping said wafer onto said platen, whilesaid electrode is biased at an initial voltage; applying a first voltageto said electrode of the platen to electrostatically clamp said wafer tosaid platen, said first voltage greater than said initial voltage;applying a second voltage to said electrode directly after applicationof said first voltage, said second voltage less than said first voltageand greater than said initial voltage; applying a third voltage to saidelectrode directly after application of said second voltage, whereinsaid third voltage is less than said second voltage and greater thansaid initial voltage; applying a fourth voltage to said electrodedirectly after application of said third voltage, wherein said fourthvoltage is greater than said third voltage and less than said firstvoltage; and applying a fifth voltage to said electrode directly afterapplication of said fourth voltage, wherein said fifth voltage is lessthan said fourth voltage and greater than said initial voltage, whereinsaid wafer is removed after application of said fifth voltage.
 2. Themethod of claim 1, wherein said wafer is removed during application of avoltage greater than said initial voltage.
 3. A method of clamping anddeclamping a wafer from a platen, comprising: placing said wafer on saidplaten, said platen comprising an electrode for clamping said wafer,while said electrode is biased at 0 volts; applying a first voltage tosaid electrode to electrostatically clamp said wafer to said platen,said first voltage between 100V and 1000V; applying a second voltage tosaid electrode directly after application of said first voltage, saidsecond voltage less than said first voltage and between 5V and 600V;applying a third voltage to said electrode directly after application ofsaid second voltage, wherein said third voltage is less than said secondvoltage and between 5V and 600 V; and applying a fourth voltage to saidelectrode directly after application of said third voltage, wherein saidfourth voltage is greater than said third voltage, less than said firstvoltage and between 5V and 600V; applying a fifth voltage to saidelectrode directly after application of said fourth voltage, whereinsaid fifth voltage is less than said fourth voltage and between 5V and600V; and removing said wafer from said platen after said application ofsaid fifth voltage to said electrode.
 4. The method of claim 3, whereinsaid first voltage is 500V; said second voltage is 250V; and said thirdvoltage is 15V.
 5. The method of claim 3, wherein said first voltage is500V; said second voltage is 350V; and said third voltage is 15V.
 6. Themethod of claim 3, wherein said first voltage is 500V; said secondvoltage is 250V; said third voltage is 15V; said fourth voltage is 250V;and said fifth voltage is 15V.
 7. The method of claim 3, wherein saidfirst voltage is 500V; said second voltage is 350V; said third voltageis 15V; said fourth voltage is 350V; and said fifth voltage is 15 V.